Cadence LDV V3.3 for Win32 (EDA 邏輯電路設計軟體)


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軟體名稱:Cadence LDV V3.3 for Win32 (EDA 邏輯電路設計軟體)
語系版本:
光碟片數:單片裝
破解說明:
系統支援:WIN 9x/WIN ME/WIN NT/WIN 2000/WIN XP/WIN 2003
軟體類型:EDA 邏輯電路設計軟體
硬體需求:PC
更新日期:2004/2/11
官方網站:
中文網站:
軟體簡介:
銷售價格:80
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破解說明:安裝說明請參見光碟\crack



軟體簡介:

Cadence LDV V3.3 for Win32 正式版
       

【軟體簡介】

      Cadence LDV is Logic Design and Verification Bundle for EDA.
      With Cadence ldv, EDA engineer can do simulation at behavior level
      using Verilog-XL,NC-Verilog or NC-VHDL. You can browse your resource,
      domostrate and compare waves quickly and browse signal  stream. 
      Also, there are code management tools like VeriSure and  VHDL Cover 
      and so on which can be used to analyze result of simulation.
      Then u can also do simulation at gate level using Buldgates.
      Verifault XL,another tool in the Bundle,can be used to dofault 
      analyzation.

      Notes: This is windows version 3.3, Cadence has removed many function
      from the bundle. It only includes SimVision and Verilog-XL. Bundle with
      full function can be found in unix version. So pls waiting for our
      Linux/Sun rls.;-)
　


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